• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a frequency-voltage conversion circuit, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result.
    公开号:US20010001543A1
    申请号:US09/757,793
    申请日:2001-01-11
    公开日:2001-05-24
    发明作者:Teruo Sasaki
    申请人:Teruo Sasaki；
    IPC主号:H03D7-166
    专利说明:
    [0001] This invention relates to a frequency-voltage conversion circuit and a receiving apparatus applicable for a direct conversion receiver which receives and demodulates a FSK Frequency Shift Keying) signal. [0001]
    [0002] A superheterodyne method and a direct conversion method are generally used in a FSK (Frequency Shift Keying) receiver. In each method, demodulation is carried out by the use of the known F-V (Frequency-Voltage) conversion. [0002]
    [0003] Referring to FIG. 1, description will be made about a related direct conversion receiver using the F-V conversion. [0003]
    [0004] In a Weber receiver illustrated in FIG. 1 the direct conversion receiver, a base-band cross signal is brought up to intermediate frequency (namely, up-conversion is conducted), and the F-V conversion is performed. [0004]
    [0005] The FSK signal sent from a receiver (not shown) is received by an antenna [0005] 101, is amplified by a high frequency amplifier 102, and is given to mixers 103 and 104, respectively.
    [0006] A local oscillator [0006] 107 produces an oscillation signal. The oscillation signal is shifted with π/2 by the use of a π/2 shifter 105, and is given to the mixer 103. Further, the frequency signal from the local oscillator 107 is directly given to the mixer 104.
    [0007] Low pass filters (hereinafter, abbreviated as LPFs) [0007] 106 and 108 are connected to the mixers 103 and 104, respectively. In this condition, output signals from the mixers 103 and 104 are given to the LPSs 106 and 108, respectively.
    [0008] Each of the LPFs [0008] 106 and 108 has passing band equivalent to the base band signal, and realizes or obtains selectivity between adjacent channels. Further, the LPFs 106 and 108 supply output signals corresponding to signals from the mixers 103 and 104 into an up-conversion portion 130.
    [0009] In this case, the up-conversion portion [0009] 130 is composed of mixers 109 and 110, a local oscillator 113, a π/2 shifter, and an adder 112, as illustrated in FIG. 1.
    [0010] With this structure, the mixer [0010] 109 is given with an oscillation signal from the local oscillator 113. Further, the oscillation signal from the local oscillator 113 is shifted with π/2 by a π/2 shifter 111, and is given to the mixer 110.
    [0011] Signals multiplied by the mixers [0011] 109 and 110 are added by the adder 112 Alternatively, the multiplied signals may be subtracted by a subtracter (not shown). An output signal of the adder 112 is converted by the use of a delay detection portion 114.
    [0012] In the above-mentioned Weber receiver [0012] 131, a carrier wave frequency of the received FSK signal is defined as π/2 π while frequency deviation is defined as ±Δω/2 λ. In this condition, the received FSK signal SrFSX is represented by the following equation.
    [0013] In this event, when the output signal S[0013] OSC1 of the local oscillator 107 is defined as SOSC1=sin ωt, the output signals SMIX3 and SMIX4 of the mixers 103 and 104 are represented by the following equations, respectively.
    [0014] First terms of these equations are removed by the LPFs [0014] 106 and 108. Therefore, the outputs SLPF8 and SLPF8 of the LPFs 106 and 108 are represented by the following equations.
    [0015] In this case, when calculation is carried out without limiter amplifiers [0015] 128 and 129 so as to be readily understood, an output signal Vout of the up-conversion portion 130 is modified as follows. Herein, it is to be noted that the output signal of the local oscillator 113 is defined by SOSC 2=sin ω2t.
    [0016] From the above-mentioned result, the base band signal I, Q is converted to a signal having frequency deviation of ±Δω/2π when the intermediate frequency ω2/2π is defined as a center. [0016]
    [0017] Subsequently, when the limiter amplifiers [0017] 128 and 129 are inserted between the LPF 106 and the mixer 109 or between the LPF 108 and the mixer 110, the condition is explained as follows.
    [0018] When inputs into the mixers [0018] 109 and 110 becomes rectangular wave by the limiter amplifiers 128 and 129, outputs SLPF6 and SLPF8, are modified as follows by Fourier transforming the above-mentioned equations (1) and (2) Herein, it is to be noted that constant is defined as k=2/π.
    [0019] Namely, the output Vout′ of the up-conversion portion [0019] 130 is similarly considered to be the modification of the above-mentioned equation (3). Thereby, the following equation is introduced.
    [0020] Vout=[0020] k{sin (ω2±ω) t +⅓·sin (3(ω2±Δω)t +⅕·sin(5(ω2±Δω)t)+. . .}  (3′)
    [0021] [0021]
    [0022] Consequently, it is found out that the conversion-up becomes possible even when the limiter amplifiers [0022] 128 and 129 are inserted between the LPF 106 and the mixer 109 or between the LPF 108 and the mixer 110.
    [0023] Although the Weber receiver [0023] 131 has been suggested as a SSB (Single Side Band) receiver, it is found out that the Weber receiver 131 is applicable as the FSK receiver, as explained above.
    [0024] The output signal of the adder [0024] 112 is given to the delay detection portion 114, and the F-V conversion is carried out in the delay detection portion 114.
    [0025] In FIG. 2, a detail structure of the delay detection portion [0025] 114 is illustrated. Further, a timing chart showing change (waveform) of each signal of each portion in the delay detection portion 114 is illustrated in FIG. 3.
    [0026] A signal V[0026] A from the adder 112 is converted into output signals VB and VC by removing amplitude demodulation components by the use of a limiter amplifier 119.
    [0027] Subsequently, the output signals V[0027] B and VC are converted into signals VD and VE having desired slopes at rising through common-emitter transistors 121 and 221. Further, the signals VD and VE are converted into signals VF and VG by comparators 123 and 223 given with threshold level VTH26 from a reference voltage 126.
    [0028] In this event, the transistors [0028] 121 and 221 are coupled to constant current sources 120, 220 and capacitors 122, 222, respectively.
    [0029] Moreover, the signals V[0029] F and VG are converted into a signal VH via an AND gate (namely logical product). Thereby, pulse signal line, which has constant amplitude and constant delay time τ is formed, as illustrated in FIG. 3.
    [0030] Finally, the pulse signal line V[0030] H is integrated by a LPF 125, and converted into a voltage value VI corresponding to frequency. Further, the obtained voltage VI is converted into a logic data signal consisting of “1” and “0” by a converter (not shown).
    [0031] In FIG. 4, frequency spectrums are illustrated so as to explain the above-mentioned structure. In an intermediate stage in the FIG. 4, center frequency between frequency of “1” and frequency of “0” becomes carrier wave frequency. [0031]
    [0032] In FIG. 5, characteristic obtained the delay detection portion [0032] 114 is illustrated. In the above-mentioned example, demodulation sensitivity KD is defined as KD=2τ V [V/Hz]. Consequently, the characteristic is affected by variation of τ and V. Herein, it is to be noted that τ represents delay time while V indicates output amplitude of the signal VH.
    [0033] Moreover, the delay time τ is inversely proportional to variation of the constant current sources [0033] 120 and 220 illustrated in FIG. 2, and is proportional to variation of static capacitance of the capacitors 122 and 222. Further, the delay time τ is proportional to the threshold voltage VTH26.
    [0034] Specifically, the demodulation sensitivity is fluctuated by variation of manufacturing condition. In addition, Further, F-V conversion output amplitude is varied in the direct-conversion method using the F-V conversion. As a result, receiving condition may be deteriorated. [0034]
    [0035] Further, the power supply voltage is restricted from the same reason, and reneality of the F-V conversion is degraded. In consequence, receiving condition is also degraded. [0035] SUMMARY OF THE INVENTION
    [0036] It is therefore an object of this invention to provide a frequency-voltage conversion circuit which is capable of correcting manufacturing variation and change with time caused by the variation. [0036]
    [0037] It is another object of this invention to provide a frequency-voltage conversion circuit which is capable of demodulating a FSK signal with stable and high sensibility and linearity. [0037]
    [0038] In a frequency-voltage conversion circuit according to this invention, integrating means gives a predetermined slope for rising or falling of a rectangular pulse signal. [0038]
    [0039] First comparing means compares an output value of the integrating means with a threshold value, and produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal. [0039]
    [0040] Storing means stores and retains the threshold value. Smoothing means smooths the pulse signal line, and produces a voltage value corresponding to the frequency of the rectangular pulse signal. [0040]
    [0041] Second comparing means compares the voltage value with a reference voltage, and charges and discharges electric charge for the storing means on the basis of the comparison result. [0041]
    [0042] In this case, the integrating means comprises a constant current device which produces constant current, and a static capacitance device which stores the current. [0042]
    [0043] With such a structure, the second comparing means discharges the electric charge from the storing means when the voltage value is higher than the reference voltage. [0043]
    [0044] On the other hand, the second comparing means charges electric charge for the storing means when the voltage value is lower than the reference voltage. [0044] BRIEF DESCRIPTION OF THE DRAWINGS
    [0045] FIG. 1 is a block diagram showing a related direct conversion receiver using F-V conversion; [0045]
    [0046] Fig. 2 is a connection diagram showing a detail structure of the delay detection portion [0046] 114 illustrated in FIG. 1;
    [0047] FIG. 3 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion [0047] 114 illustrated in FIG. 1;
    [0048] FIG. 4 is diagram showing frequency spectrums for explaining function of the direct-conversion receiver; [0048]
    [0049] FIG. 5 is a characteristic diagram showing characteristic obtained by the delay detection portion [0049] 114 illusrated in FIG. 1;
    [0050] FIG. 6 is a block diagram showing a structure of a receiver according to a first embodiment of this invention; [0050]
    [0051] FIG. 7 is a connection diagram showing a detail structure of the delay detection portion [0051] 14 illustrated in FIG. 6;
    [0052] FIG. 8 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion [0052] 14 illustrated in FIG. 6;
    [0053] FIG. 9 is a characteristic diagram showing difference of F-V conversion characteristic (demodulation sensitivity) due to difference of threshold level V[0053] TH16;
    [0054] FIG. 10 is a connection diagram showing a detail structure of a delay detection portion [0054] 14 in frequency-voltage conversion circuit according to a second embodiment of this invention; and
    [0055] FIG. 11 is a timing chart showing change (waveform) of each signal of each portion in the delay detection portion illustrated in FIG. 10. [0055] DESCRIPTION OF THE PREFERRED EMBODIMENTS
    [0056] Hereinafter, description will be made about embodiments of this invention with drawings. [0056]
    [0057] (First embodiment) [0057]
    [0058] Referring to FIG. 6, description will be made about a first embodiment of this invention. [0058]
    [0059] A FSK (Frequency Shift Keying) signal transmitted from a transmitter (not shown) is received via an antenna [0059] 1, is amplified by a high-frequency amplifier 2 ,and is given to mixers 3 and 4, respectively.
    [0060] An oscillation signal from a local oscillator [0060] 7 is shifted with 2/π by a 2/π shifter 5. The shifted signal is given to the mixer 3 while the oscillation signal from the local oscillator 7 is directly given to the mixer 4.
    [0061] The mixers [0061] 3 and 4 are connected to LPFs (Low Pass Filters) 6 and 8 as channel filters, respectively. Output signals of the mixers 3 and 4 are given to the LPFs 6 and 8.
    [0062] Each of the LPFs [0062] 6 and 8 has passing band equivalent to a base band signal, and realizes or obtains selectivity between adjacent channels. Further, the LPFs 6 and 8 supply output signals corresponding to signals from the mixers 3 and 4 into an up-conversion portion 30.
    [0063] The up-conversion portion [0063] 30 is composed of a mixer 9, a mixer 10, a local oscillator 13, a 2/π shifter 11, and an adder 12. The mixer 9 is given with an oscillation signal from the local oscillator 13. On the other hand, the oscillation signal from the local oscillator 13 is shifted with 2/π by the 2/π shifter 5. The shifted signal is given to the mixer 10.
    [0064] Signals multiplied by the mixers [0064] 9 and 10 are added by the use of an adder 12. Alternatively, the multiplied signals may be subtracted by a subtracter (not shown).
    [0065] The reference numeral [0065] 32 represents a switch which switches a signal obtained by a Weber receiver 31 with an output signal of the local oscillator 13. The reference numeral 14 indicates a delay detection portion which F-V converts an output signal of the switch 32. Further, the reference numeral 18 represents a control portion which controls the switch 32 and the delay detection portion 14.
    [0066] The switch [0066] 32 gives the output signal of the local oscillator 13 into the delay detection portion 14 when a control signal S18 is put into “H” (high level). On the other hand, the switch 32 gives the output signal of the adder 12 into the delay detection portion 14 when the control signal S18 is put into “L” (low level).
    [0067] In FIG. 7, a signal V[0067] A (rectangular pulse signal) from the above adder 12 is removed amplitude modulation components thereof by a limiter amplifier 19, and is converted into output signals VB and VC respectively.
    [0068] Subsequently, the output signals V[0068] B and VC are converted into signals VD and VE having desired slopes at rising through common-emitter transistors 21 a and 21 b. Herein, it is to be noted that each of the signals VD and VE may have the slope at falling.
    [0069] Further, the signals V[0069] D and VE are converted into signals VF and VG by comparators 23 a and 23 b.
    [0070] In this event, the transistors [0070] 21 a and 21 b are coupled to constant current sources 20 a, 20 b and capacitors 22 a, 22 b, respectively. The comparators 23 a and 23 b are coupled to a capacitor 16, and is given with an output signal of a VI amplifier 15.
    [0071] Further, the signals V[0071] F and VG are converted into a signal VH via an AND gate (logical product). Thereby, a pulse signal line VH, which has constant amplitude and constant delay time τ, is formed, as illustrated in FIG. 8.
    [0072] The pulse signal line V[0072] H is integrated by a LPF 25, and is converted into a voltage value VI corresponding to frequency.
    [0073] Further, the voltage value V[0073] I is compared with a reference voltage 17 (VREF). An output signal of the VI amplifier 15 is supplied as a reference voltage of the comparator 23 a, 23 b.
    [0074] With such a structure, when the control signal S[0074] 18 is put into “L” (low level), the switch 32 selects the output of the adder 32. Consequently, the VI amplifier 15 is put into an off-state (namely, an output terminal is opened). Consequently, electric charge (threshold level VTH16) of the capacitor 16 is retained or kept.
    [0075] On the other hand, when the control signal S[0075] 18 is put into “H” (high level), the switch 32 selects the output signal of the local oscillator 32. As a result, the VI amplifier 15 is put into an on-state. Thereby, feedback in the delay detection portion 14 is activated.
    [0076] As mentioned above, the signal V[0076] A from the delay detection portion 14 is removed the amplitude modulation components thereof by the limiter amplifier 19, and is converted into the signals VB and VC. In this event, the signals VB and VC have phases reverse to each other.
    [0077] Subsequently, the output signals V[0077] B and VC are converted into signals VD and VE by the common-emitter transistors 21 a and 21 b, and further, converted into signals VF and VG by the comparators 23 a and 23 b. Herein, it is to be noted that each of the comparators 23 a and 23 b has the threshold level VTH16.
    [0078] Further, the signals V[0078] F and VG are converted into a signal VH by via the AND gate. Thereby, pulse signal line VH having the constant amplitude and the constant delay time τ is formed, as described before.
    [0079] Finally, the pulse signal line V[0079] H is integrated by the LPF 25, and is converted into the voltage value VI corresponding to the frequency of the signal VA.
    [0080] The voltage value V[0080] I is compared with the reference voltage VREF. As a result of the comparison, when the voltage value VI is higher than the reference voltage VREF, the output of the VI amplifier 15 is put into “L”. Thereby, electric charge off the capacitor 16 is discharged. In consequence, the threshold level VTH16 is lowered or reduced.
    [0081] On the other hand, when the voltage value V[0081] I is lower than the reference voltage VREF, the output of the VI amplifier 15 is put into “H”. Thereby, electric charge of the capacitor 16 is charged. Thereby, the threshold level VTH16 is increased.
    [0082] In the first embodiment, the delay time τ is adjusted on the condition that the control signal S[0082] 18 is put into “H”. Thereby, the voltage value VI from the delay detection portion 14 is converged to the reference voltage VREF. In this event, frequency given to the delay detection portion 14 is equal to center frequency of a second FSK signal.
    [0083] On the other hand, when the control signal S[0083] 18 is put into “L”, a normal receiving state appears. In this case, frequency given to the delay detection portion 14 is equal to the second FSK signal. Therefore, the control signal S18 is put into “H” during signal receiving wait state or during signal receiving state unnecessary to receive a signal.
    [0084] The above-mentioned delay time τ is inversely proportional to current variation of the constant current source [0084] 20 a, 20 b. Further, the delay time τ is proportional to variation of static capacitance of the capacitor 22 a, 22 b, and is proportional to the threshold voltage VTH16 as the reference voltage given to the comparator 23 a, 23 b.
    [0085] In this embodiment, when the voltage value V[0085] I is higher than the reference voltage VREF, the delay time τ becomes higher than a value to be essential. In this case, the VI amplifier 15 discharges electric charge of the capacitor 16 so as to reduce VTH16. Thereby, the delay time τ becomes low. In consequence, the voltage value VI is reduced, and the voltage value VI is finally is converged to VREF.
    [0086] On the other hand, when the voltage value V[0086] I is lower than the reference voltage VREF, the delay time τ becomes lower than the value to be essential. In this event, the VI amplifier 15 charges electric charge of the capacitor 16 so as to increase VTH16. Thereby, the delay time τ becomes high. Consequently, the voltage value VI is increased, and the voltage value VI is finally is converged to VREF.
    [0087] In FIG. 9, F-V conversion characteristic (demodulation sensibility) is illustrated in accordance with difference of the threshold levels V[0087] TH16.
    [0088] Herein, it is to be noted that each straight line A, B and C in FIG. 9 corresponds to each level A, B and C illustrated in FIG. 8. [0088]
    [0089] The voltage value V[0089] I is equal to a voltage corresponding to center frequency of the second FSK signal. Therefore, the voltage corresponding to the center frequency is compatible with the reference voltage VREF. Thereby, variation of the demodulation sensibility is substantially eliminated, and the F-V conversion characteristic is corrected as the straight line B illustrated in FIG. 9.
    [0090] When the receiving sate becomes normal by putting the control signal S[0090] 18 into “L”, the reference voltage VREF is used as reference voltage of a comparator or an A/D (Analog/Digital) converter given with the voltage VI, and thereby, corresponds to center frequency of accurate second FSK signal.
    [0091] (Second embodiment) [0091]
    [0092] Referring to FIG. 10, description will be made about a second embodiment of this invention. Herein, it is to be noted that the same reference numeral is attached to the same portion as each portion illustrated in FIG. 7. [0092]
    [0093] In the second embodiment, a current control portion [0093] 27 is controlled by the use of a control signal S18 from the control portion 18. The current control portion 27 compares the voltage value VI with the reference voltage VREF, and controls constant current sources 40 a and 40 b on the basis of the comparing result via the feedback.
    [0094] With such a structure, when the control signal S[0094] 18 is put into “L”(low level), current value of the constant current source 40 a, 40 b is kept to a constant value. On the other hand, when the control signal S18 is put into “HH”(high level), the output of the local oscillator 13 selected by the switch 32 is given thereto. Thereby, the current control portion 27 is put into an on-state. Consequently, the feedback becomes active.
    [0095] In this event, a signal V[0095] A is removed amplitude modulation components thereof by the limiter amplifier 19, and is converted into signals VB and VC. The signals VB and VC are given with desired slopes corresponding to current values determined by constant current sources 40 a and 40 b, and are converted into signals VD and VE.
    [0096] Further, the signals V[0096] D and VE are converted into signals VF and VG by comparators 23 a and 23 b. In this event, each of the comparators are given with threshold level VTH26.
    [0097] Further, logic product (negative logic product) is carried out for the signals V[0097] F and VG through an AND gate 24. Thereby, pulse signal line VH is generated, as illustrated in FIG. 11.
    [0098] In the pulse signal line V[0098] H, amplitude and delay time τ are constantly kept. This signal line VH is integrated by a LPF 25, and is converted into voltage value VI corresponding to the frequency of the signal VA.
    [0099] In this case, the voltage value V[0099] I is compared with the reference voltage VREF. As the result of the comparison, when the voltage value VI is higher than the reference voltage VREF, the current control portion 27 controls so as to increase current value of the constant current source 40 a, 40 b.
    [0100] On the other hand, when the voltage value V[0100] I is lower that the reference voltage VREF, the current control portion 27 controls so as to reduce the current value of the constant current source 40 a, 40 b.
    [0101] More specifically, when the control signal S[0101] 18 is put into “H” (namely, the feedback is in an active state), the delay time τ is adjusted. Further, the F-V converted voltage value VI is converged into the reference voltage VREF. On the other hand, when the control signal S18 is put into “L”, normal receiving state appears.
    [0102] Therefore, the control signal S[0102] 18 is put into “H” so as to perform the feedback during signal receiving wait state or during signal receiving state unnecessary to receive a signal.
    [0103] The delay time τ is inversely proportional to variation of the current value of the constant current source [0103] 40 a, 40 b, and is proportional to static capacitance of the capacitor 22 a, 22 b. Further, the delay time τ is proportional to the threshold level VTH26 given to the comparator 23 a, 23 b.
    [0104] In this embodiment, when the voltage value V[0104] I is higher than the reference voltage VERF, the delay time τ is becomes larger than a value to be essential. In such a case, the current control portion 27 controls so as to increase the current value of the constant current source 40 a, 40 b. Thereby, the voltage value VI becomes low, and the voltage value VI finally converges into VREF.
    [0105] On the other hand, when the voltage value V[0105] I is lower than the reference voltage VERF, the delay time τ is becomes lower than the value to be essential. In this case, the current control portion 27 controls so as to reduce the current value of the constant current source 40 a, 40 b. Thereby, the voltage value VI becomes large, and the voltage value VI finally converges into VREF.
    [0106] Herein, it is to be noted that the voltage value V[0106] I is a voltage which corresponds to center frequency of the second FSK signal. Therefore, the voltage corresponding to the center frequency is made to be compatible with the referential voltage VREF. Thereby, variation of demodulation sensibility is substantially eliminated. Further, the F-V conversion characteristic is corrected as the straight line B illustrated in FIG. 9 When the control signal S18 is put into “L” and is in the normal receiving state, the reference voltage VREF is used as the reference voltage of a comparator or a A/D converter which is supplied with the voltage value VI, and thereby, accurately corresponds to the center frequency of the second FSK signal.
    权利要求:
    Claims (15)
    [1" id="US-20010001543-A1-CLM-00001] 1. A frequency-voltage conversion circuit, comprising:
    integrating means which gives a predetermined slope for rising, or falling of a rectangular pulse signal;
    first comparing means which compares an output value of the integrating means with a threshold value and which produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal;
    storing means which stores and retains the threshold value;
    smoothing means which smooths the pulse signal line and which produces a voltage value corresponding to the frequency of the rectangular pulse signal; and
    second comparing means which compares the voltage value with a reference voltage and which charges and discharges electric charge for the storing means on the basis of the comparison result.
    [2" id="US-20010001543-A1-CLM-00002] 2. A circuit as claimed in
    claim 1 , wherein:
    the integrating means comprises;
    a constant current device which produces constant current, and
    a static capacitance device which stores the current.
    [3" id="US-20010001543-A1-CLM-00003] 3. A circuit as claimed in
    claim 1 , wherein:
    the second comparing means discharges the electric charge from the storing means when the voltage value is higher than the reference voltage.
    [4" id="US-20010001543-A1-CLM-00004] 4. A circuit as claimed in
    claim 1 , wherein:
    the second comparing means charges electric charge for the storing means when the voltage value is lower than the reference voltage.
    [5" id="US-20010001543-A1-CLM-00005] 5. A frequency-voltage conversion circuit, comprising:
    integrating means which gives a predetermined slope for rising or falling of a rectangular pulse signal;
    comparing means which compares an output value of the integrating means with a threshold value and which produces a pulse signal line having a pulse width corresponding to frequency of the rectangular pulse signal;
    smoothing means which smooths the pulse signal line and which produces a voltage value corresponding to the frequency of the rectangular pulse signal; and
    a current control portion which compares the voltage value with a reference voltage and which changes the slope of the rising or the falling of the rectangular pulse signal on the basis of the comparison result.
    [6" id="US-20010001543-A1-CLM-00006] 6. A circuit as claimed in
    claim 5 , wherein:
    the integrating means comprises;
    a constant current device which restricts current to a predetermined value, and
    a static capacitance device which stores the current.
    [7" id="US-20010001543-A1-CLM-00007] 7. A circuit as claimed in
    claim 6 , wherein the
    the current control portion compares the voltage value with the reference voltage and changes current restricting value by the constant current device on the basis of the comparison result.
    [8" id="US-20010001543-A1-CLM-00008] 8. A circuit as claimed in
    claim 7 , wherein:
    the current control portion increases the current restricting value by the constant current device when the voltage value is higher than the reference voltage.
    [9" id="US-20010001543-A1-CLM-00009] 9. A circuit as claimed in
    claim 7 , wherein:
    the current control portion reduces the current restricting value by the constant current device when the voltage value is lower than the reference voltage.
    [10" id="US-20010001543-A1-CLM-00010] 10. A receiving apparatus having at least an oscillator, and an up-conversion portion which includes a first mixer connected to the oscillator, a second mixer connected to the oscillator via a 2/π shifter, and an adder for adding output signals of the first and second mixers, comprising:
    a switch which selects either one of an output signal of the oscillator and an output signal of the adder;
    a delay detection portion which converts the selected signal between frequency and voltage so as to produce a voltage value; and
    control portion which controls the switch and the delay detection portion.
    [11" id="US-20010001543-A1-CLM-00011] 11. An apparatus as claimed in
    claim 10 , wherein:
    the control portion gives a control signal into the switch and the delay detection portion.
    [12" id="US-20010001543-A1-CLM-00012] 12. An apparatus as claimed in
    claim 11 , wherein:
    the control portion selects the output signal of the oscillator when the control signal is put into a first level while the control portion selects the output signal of the adder when the control signal is put into a second level different from the first level.
    [13" id="US-20010001543-A1-CLM-00013] 13. An apparatus as claimed in
    claim 12 , wherein:
    the first level is equal to a high level while the second level is equal to a low level.
    [14" id="US-20010001543-A1-CLM-00014] 14. An apparatus as claimed in
    claim 10 , wherein:
    the oscillator produces a rectangular pulse signal having a predetermined frequency.
    [15" id="US-20010001543-A1-CLM-00015] 15. An apparatus as claimed in
    claim 10 , wherein: the receiving apparatus includes a Weber receiver.
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    法律状态:
    2002-07-25| STCF| Information on status: patent grant|Free format text: PATENTED CASE |
    2006-01-20| FPAY| Fee payment|Year of fee payment: 4 |
    2010-01-14| FPAY| Fee payment|Year of fee payment: 8 |
    2014-01-15| FPAY| Fee payment|Year of fee payment: 12 |
    2014-09-11| AS| Assignment|Owner name: LENOVO INNOVATIONS LIMITED (HONG KONG), HONG KONG Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:033720/0767 Effective date: 20140618 |
    优先权:
    申请号 | 申请日 | 专利标题
    JP353813/1998||1998-11-30||
    JP35381398A|JP3204233B2|1998-11-30|1998-11-30|Frequency-voltage conversion circuit, receiver, and method of controlling frequency-voltage conversion characteristics|
    US09/450,331|US6252438B1|1998-11-30|1999-11-29|Frequency-voltage conversion circuit and receiving apparatus|
    US09/757,793|US6433591B2|1998-11-30|2001-01-11|Frequency-voltage conversion circuit and receiving apparatus|US09/757,793| US6433591B2|1998-11-30|2001-01-11|Frequency-voltage conversion circuit and receiving apparatus|
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